Semiconductor device and method of manufacturing thereof

ABSTRACT

A part of the semiconductor substrate is processed to form fins protruding from the upper surface of the semiconductor substrate. Next, an interlayer insulating film is formed on the semiconductor substrate including the fin FA, and an opening is formed in the interlayer insulating film. Next, a dummy pattern including the dummy material and the insulating film is formed in the opening in a self-aligned manner. Thereafter, the dummy pattern is replaced with a memory gate electrode, a control gate electrode, and the like.

CROSS-REFERENCE TO RELATED APPLICATIONS

The disclosure of Japanese Patent Application No. 2018-123268 filed onJun. 28, 2018 including the specification, drawings and abstract isincorporated herein by reference in its entirety.

BACKGROUND

The present invention relates to a semiconductor device and method ofmanufacturing thereof, and more particularly, to a technique effectivefor application to a semiconductor device including a fin structuretransistor.

Flash memories or EEPROM (Electrically Erasable and Programmable ReadOnly Memory) are widely used as electrically writable and erasablenonvolatile memories. These storage devices have a conductive floatinggate electrode or a trapping insulating film surrounded by an oxide filmbelow the gate electrode of MISFET (Metal Insulator Semiconductor FieldEffect Transistor), and the charge accumulation state in the floatinggate or the trapping insulating film is used as storage information,which is read out as a threshold of the transistor. The trappinginsulating film refers to an insulating film capable of accumulatingcharges, and as an example, a silicon nitride film or the like can begiven. By shifting the threshold of the MISFET by injecting anddischarging charges into/from the charge storage layers, the MISFET canbe used as a nonvolatile memory. This flash memory is also referred toas a MONOS (Metal Oxide Nitride Oxide Semiconductor type transistor. Inaddition, split-gate memory cells in which a MONOS transistor is used asa memory transistor and a control transistor is further added are widelyused.

In addition, a fin-structure transistor is known as a field-effecttransistor capable of increasing an operation speed, reducing a leakagecurrent and power consumption, and miniaturizing a semiconductorelement. The fin-structure transistor (FinFET: Fin Field EffectTransistor) is, for example, a semiconductor element having asemiconductor layer protruding from a semiconductor substrate as achannel region, and having a gate electrode formed so as to stride overthe semiconductor layer substrate protruded.

Japanese Unexamined Patent Application Publication No. 2006-41354discloses a split-gate memory cell having a MONOS transistor.

Japanese Unexamined Patent Application Publication No. 2017-45860discloses a technique of forming a MONOS transistor as a fin-structuretransistor. A technique is disclosed in which a control gate electrodeis formed by patterning, then a polycrystalline silicon film is formedso as to cover the control gate electrode, and anisotropic etching isperformed on the polycrystalline silicon film to form a memory gateelectrode in the shape of a sidewall spacer on the side surface of thecontrol gate electrode.

Japanese Unexamined Patent Application Publication No. 2014-127527discloses a split-gate memory cell having a MONOS transistor. Atechnique of forming a control gate electrode in a region where thedummy pattern is removed, that is, a technique called “gate last” isdisclosed.

SUMMARY

In the fin structure transistor, many steps are generated by the finsprotruding from the semiconductor substrate. Therefore, when a pluralityof gate electrodes is formed as in a split gate type memory cell, anetching process having a high aspect ratio is required in some casesdepending on the height of the fin, and it is difficult to form eachgate electrode. In addition, there may be an isolated pattern having afine gate length during the manufacturing process, but as theminiaturization of the semiconductor element progresses, it is importantto suppress the collapse of such an isolated pattern.

Other objects and novel features will become apparent from thedescription of the specification and the accompanying drawings.

The typical ones of the embodiments disclosed in the present applicationwill be briefly described as follows.

The method of manufacturing a semiconductor device according to theembodiment includes a step of preparing a semiconductor substrate, astep of forming a first interlayer insulating film on the semiconductorsubstrate, a step of forming a first opening in the first interlayerinsulating film, a step of forming a dummy pattern in the first opening,a step of removing a part of the dummy pattern, and a step of fillingthe first opening from which the part of the dummy pattern is removedwith the first gate electrode. The method of manufacturing asemiconductor device further includes a step of removing the dummypattern left in the first opening, and a step of filling the first holefrom which the dummy pattern is removed with the second gate electrode.

According to one embodiment, the yield of the semiconductor device canbe improved.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a plan view illustrating a semiconductor device according tothe first embodiment.

FIG. 2 is a perspective view illustrating a semiconductor deviceaccording to a first embodiment;

FIG. 3 is a cross-sectional view illustrating a semiconductor deviceaccording to the first embodiment.

FIG. 4 is a cross-sectional view illustrating a semiconductor deviceaccording to the first embodiment.

FIG. 5 is a diagram illustrating an example of a non-volatile memorymodule;

FIG. 6 is a table illustrating an example of a condition for applying avoltage to each part of a selected memory cell during “write”, “erase”and “read”.

FIG. 7 is a plan view illustrating a manufacturing process of asemiconductor device according to the first embodiment;

FIG. 8 is a cross-sectional view illustrating a manufacturing process ofa semiconductor device according to the first embodiment.

FIG. 9 is a cross-sectional view illustrating a manufacturing processfollowing FIG. 8.

FIG. 10 is a cross-sectional view illustrating a manufacturing processfollowing FIG. 9.

FIG. 11 is a cross-sectional view illustrating a manufacturing processfollowing FIG. 10.

FIG. 12 is a cross-sectional view illustrating a manufacturing processfollowing FIG. 11.

FIG. 13 is a cross-sectional view illustrating a manufacturing processfollowing FIG. 12.

FIG. 14 is a cross-sectional view illustrating a manufacturing processfollowing FIG. 13.

FIG. 15 is a cross-sectional view illustrating a manufacturing processfollowing FIG. 14.

FIG. 16 is a cross-sectional view illustrating a manufacturing processfollowing FIG. 15.

FIG. 17 is a cross-sectional view illustrating a manufacturing processfollowing FIG. 16.

FIG. 18 is a cross-sectional view illustrating a manufacturing processfollowing FIG. 17.

FIG. 19 is a cross-sectional view illustrating a manufacturing processfollowing FIG. 18.

FIG. 20 is a perspective view at the time of completion of themanufacturing process of FIG. 19.

FIG. 21 and FIG. 20 are cross-sectional views illustrating amanufacturing process following FIGS. 19 and 20.

FIG. 22 is a cross-sectional view illustrating a manufacturing processfollowing FIG. 21.

FIG. 23 is a cross-sectional view illustrating a manufacturing processfollowing FIG. 22.

FIG. 24 is a cross-sectional view illustrating a manufacturing processfollowing FIG. 23.

FIG. 25 is a cross-sectional view illustrating a manufacturing processfollowing FIG. 24.

FIG. 26 is a cross-sectional view illustrating a manufacturing processfollowing FIG. 25.

FIG. 27 is a cross-sectional view illustrating a manufacturing processfollowing FIG. 26.

FIG. 28 is a cross-sectional view illustrating a manufacturing processof the semiconductor device of First Modified Example.

FIG. 29 is a cross-sectional view illustrating a manufacturing processfollowing FIG. 28.

FIG. 30 is a sectional view illustrating a manufacturing processfollowing FIG. 29.

FIG. 31 is a cross-sectional view illustrating a manufacturing processfollowing FIG. 30.

FIG. 32 is a plan view illustrating a manufacturing process of asemiconductor device according to a second modified example;

FIG. 33 is a plan view illustrating a manufacturing process of asemiconductor device according to a third modified example;

FIG. 34 is a plan view illustrating a manufacturing process of asemiconductor device according to a fourth modified example;

FIG. 35 is a plan view illustrating a manufacturing process followingFIG. 34.

FIG. 36 is a plan view illustrating a manufacturing process of asemiconductor device according to a fifth modified example;

FIG. 37 is a plan view illustrating a manufacturing process of asemiconductor device according to a sixth modified example;

FIG. 38 is a cross-sectional view illustrating a manufacturing processof a semiconductor device according to the second embodiment.

FIG. 39 is a cross-sectional view illustrating a manufacturing processfollowing FIG. 38.

FIG. 40 is a sectional view illustrating a manufacturing process of asemiconductor device according to a seventh modified example;

DETAILED DESCRIPTION

In the following embodiments, if necessary for the sake of convenience,the embodiments will be each described by being divided into a pluralityof sections or embodiments. However, they are by no means irrelevant toeach other unless particularly explicitly described otherwise, but arein relations such that one of the sections or embodiments is a modifiedexamples, details, supplementary explanation, and so forth of part orthe whole of the others. Also, in the following embodiments, when thenumber and the like (including the number, numerical value, amount,range, and the like) of elements are referred to, they are not limitedto specific numbers unless particularly explicitly described otherwiseor unless they are obviously limited to specific numbers in principle.The number and the like of the elements may be not less than or not morethan specific numbers.

Furthermore, in the following embodiments, when the number and the like(including the number, numerical value, amount, range, and the like) ofelements are referred to, they are not limited to specific numbersunless particularly explicitly described otherwise or unless they areobviously limited to specific numbers in principle. The number and thelike of the elements may be not less than or not more than specificnumbers. Also, in the following embodiments, it goes without saying thatthe components thereof (including also elements, steps, and the like)are not necessarily indispensable unless particularly explicitlydescribed otherwise or unless the components are considered to beobviously indispensable in principle. Likewise, if the shapes,positional relationships, and the like of the components and the likeare referred to in the following embodiments, the shapes and the likeare assumed to include those substantially proximate or similar theretoand the like unless particularly explicitly described otherwise orunless it can be considered that they obviously do not in principle. Thesame shall apply in regard to the foregoing numerical value and range.

The following will describe embodiments in detail on the basis of thedrawings. Note that, throughout all the drawings for illustrating theembodiments, members having the same functions are designated by thesame reference numerals, and a repeated description thereof is omitted.In the following embodiments, a description of the same or like partswill not be repeated in principle unless particularly necessary.

First Embodiment

A semiconductor device including a memory cell (nonvolatile memory cell)MC of a transistor having a fin structure in this embodiment will bedescribed with reference to the drawings. FIG. 1 is a plan view of amemory cell MC. FIG. 2 is a perspective view of the memory cell MC. FIG.3 shows a cross-sectional view corresponding to line A-A and line B-B ofFIG. 1, and FIG. 4 shows a cross-sectional view corresponding to lineC-C and line D-D of FIG. 1.

Note that although the semiconductor device of this embodiment includesa logic circuit, an analogue circuit, a SRAM circuit, an input/outputcircuit, and the like in addition to the memory cell MC described above,the semiconductor device of this embodiment is characterized mainly bythe memory cell MC, and therefore, detailed descriptions of othercircuits are omitted.

Structure of Semiconductor Device

The structure of the memory cell MC of the present embodiment will bedescribed below with reference to FIGS. 1 to 4.

An insulating film SO1, an insulating film SN1, an insulating film SO3,an interlayer insulating film IL1, an interlayer insulating film IL2,and a plug PG3 are formed on each memory cell MC as described later, butthese are omitted in FIGS. 1 and 2 in order to show main parts of thememory cell MC in an easy-to-understand manner.

In plan view, a plurality of fins FA extending in the X direction arearranged on the semiconductor substrate SB at equal intervals in the Ydirection. The X direction and the Y direction are directions along themain surface of the semiconductor substrate SB, and the X direction isorthogonal to the Y direction. The length of the fin FA in the Xdirection is longer than the length of the fin FA in the Y direction.That is, the X direction is the long side direction of the fin FA, andthe Y direction is the short side direction of the fin FA. The fin FA isa part of the semiconductor substrate SB, and is a protrusion in theshape of a rectangular parallelepiped that selectively protrudes fromthe upper surface of the semiconductor substrate SB.

An element isolation portion STI is formed in the semiconductorsubstrate SB between the plurality of fins FA. The position of the uppersurface of the element isolation portion STI is lower than the positionof the upper surface of the fin FA. In other words, a part of the fin FAprotrudes from the element isolation portion STI, and the other part ofthe fin FA is positioned so as to be sandwiched by the element isolationportion STI in the Y direction. As described above, the upper portion ofeach fin FA is insulated and isolated by the element isolation portionSTI. In the present embodiment, the fin FA located higher than the uppersurface of the element isolation portion STI may be referred to as theupper portion of the fin FA, and the fin FA located lower than the uppersurface of the element isolation portion STI may be referred to as thelower portion of the fin FA.

The upper portion of the fin FA is mainly an active region for formingthe memory cell MC. That is, in the semiconductor substrate SB, a regionpartitioned by the element isolation portion STI is an active region.

The fin FA does not necessarily have to be a rectangular parallelepiped,and the corners of the rectangle may be rounded when viewed in crosssection in the Y direction. The side surface of the fin FA may beperpendicular to the main surface of the semiconductor substrate SB, ormay have an inclination angle close to perpendicular to the main surfaceof the semiconductor substrate SB.

A plurality of memory gate electrodes MG and a plurality of control gateelectrodes CG extending in the Y direction are arranged on the pluralityof fins FA. The plurality of memory gate electrodes MG and the pluralityof control gate electrodes CG are formed so as to cover the uppersurface and the side surface of the fins FA via the gate insulating filmGF1 and the gate insulating film GF2, respectively.

An n-type diffusion region MD is formed as a drain region in the fin FAon the control gate electrode CG side, and an n-type diffusion region MSis formed as a source region in the fin FA on the memory gate electrodeMG side. The diffusion region MD and the diffusion region MS are formedso as to sandwich a channel region, which is a portion of the fin FAcovered with the control gate electrode CG and the memory gate electrodeMG, in the X direction. That is, in the X direction, one control gateelectrode CG and one memory gate electrode MG are located between thediffusion region MS and the diffusion region MD.

The diffusion region MD is formed between two control gate electrodes CGadjacent to each other in the X direction, and the diffusion region MSis formed between two memory gate electrodes MG adjacent to each otherin the X direction. As described above, the two memory cells MC adjacentin the X direction share the diffusion region MD or the diffusion regionMS. Two memory cells MC sharing the diffusion region MD have linesymmetry in the X direction with the diffusion region MD as an axis, andtwo memory cells MC sharing the diffusion region MS have line symmetryin the X direction with the diffusion region MS as an axis.

The memory cell MC of the present embodiment is a MISFET having a memorygate electrode MG, a gate insulating film GF1, a control gate electrodeCG, a gate insulating film GF2, a diffusion region MD, and a diffusionregion MS, and is a nonvolatile memory cell.

A plug PG1 is formed on the diffusion region MD, and a plug PG2 isformed on the diffusion region MS. The plug PG2 extends in the Ydirection so as to commonly connect the diffusion regions MS of thememory cells MC adjacent to each other in the Y direction.

Hereinafter, the cross-sectional structure of the semiconductor deviceof the present embodiment will be described in detail with reference toFIGS. 3 and 4.

A well region PW, which is a semiconductor region having p-typeconductivity, is formed in the semiconductor substrate SB including thefin FA.

The upper surface and the side surface of the fin FA are covered with aninterlayer insulating film IL1. A opening CH2 is formed in theinterlayer insulating film IL1, and a memory gate electrode MG is formedvia the gate insulating film GF1 and a control gate electrode CG isformed via the gate insulating film GF2 so as to fill the opening CH2.That is, like the memory gate electrode MG and the control gateelectrode CG, the opening CH2 extends in the Y direction shown in FIG.1.

In the X direction, a gate insulating film GF1 and a gate insulatingfilm GF2 exist between the memory gate electrode MG and the control gateelectrode CG, and the control gate electrode CG and the memory gateelectrode MG are electrically separated by the gate insulating film GF1and the gate insulating film GF2. The gate insulating film GF1 iscontinuously formed so as to cover both side surfaces and the bottomsurface of the memory gate electrode MG, and the gate insulating filmGF2 is continuously formed so as to cover both side surfaces and thebottom surface of the control gate electrode CG.

The gate insulating film GF1 is formed on the upper surface of the finFA so as to cover the upper surface and the side surface of the fin FA,and is also formed on the upper surface of the element isolation portionSTI between two adjacent fins FA. Although not shown, the gateinsulating film GF2 is also formed in the same manner as the gateinsulating film GF1.

As described above, the memory gate electrode MG, the gate insulatingfilm GF1, the control gate electrode CG, and the gate insulating filmGF2 extend in the Y direction so as to extend over the plurality ofmemory cells MC.

In the present embodiment, the gate insulating film GF1 is formed of alaminated film including an insulating film X1, a charge storage layerCSL formed on the insulating film X1, and an insulating film X2 formedon the charge storage layer CSL.

The insulating film X1 is formed on the upper surface and the sidesurface of the fin FA, is an insulating film such as a silicon oxidefilm, for example, and has a thickness of about 2 to 4 nm.

The charge storage layer CSL is formed on the upper surface and the sidesurface of the fin FA via the insulating film X1, and is also formed onthe upper surface of the element isolation portion STI between twoadjacent fins FA. The charge storage layer CSL is a film provided forstoring data of the memory cell MC, and is an insulating film having atrap level capable of holding charge. As the insulating film having sucha trap level, for example, a silicon nitride film can be given. Thethickness of the charge storage layer CSL is about 5 to 7 nm. As anothermaterial of the insulating film having the trapping level, for example,a metal oxide film containing hafnium (Hf) and silicon (Si), such as ahafnium silicate film (HfSiO film), can be used.

The insulating film X2 is formed on the upper surface and the sidesurface of the fin FA via the insulating film X1 and the charge storagelayer CSL, and is, for example, a silicon oxide film or a metal oxidefilm such as an alumina film (AlO film), and has a thickness of about 5to 7 nm. The insulating film X2 is a film provided to improve thedielectric strength between the charge storage layer CSL and the memorygate electrode MG.

In the present embodiment, the insulating film X1, the charge storagelayer CSL, and the insulating film X2 are not shown in detail for thesake of clarity, and these laminated films are shown as the gateinsulating film GF1.

The memory gate electrode MG is a conductive film formed on the uppersurface and the side surface of the fin FA via the gate insulating filmGF1. As such a conductive film, for example, a polycrystalline siliconfilm into which an n-type impurity is introduced can be used. Instead ofthe polycrystalline silicon film, the memory gate electrode MG may be asingle-layer metal film made of tantalum nitride film, or of an aluminumfilm, or a laminated film in which these films are appropriatelystacked. The gate insulating film GF2 is a so-called high dielectricconstant film (High-k film) made of a metallic oxide film and having adielectric constant higher than that of silicon oxide. The gateinsulating film GF2 is an oxide film containing hafnium, such as ahafnium oxide film (HfO₂), and has a thickness of 1 nm to 2 nm. Asilicon oxide film having a thickness of about 1 nm may be formedbetween the gate insulating film GF2 and the fin FA as an insulatingfilm for stabilizing the interface state.

The control gate electrode CG is, for example, a single-layer metal filmmade of a tantalum nitride film, or of an aluminum film, or a laminatedfilm in which these films are appropriately stacked.

An n-type diffusion region MD is formed as a drain region in the fin FAon the control gate electrode CG side, and an n-type diffusion region MSis formed as a source region in the fin FA on the memory gate electrodeMG side.

On the diffusion region MD and the diffusion region MS, laminated filmsof an insulating film SO1, an insulating film SN1, an insulating filmSO3, and an interlayer insulating film IL1 are formed. In the Xdirection, the laminated film are formed between the memory gateelectrodes MG adjacent to each other and between the control gateelectrodes CG adjacent to each other. The upper surface of theinterlayer insulating film IL1 is polished by the Chemical MechanicalPolishing method. Therefore, the interlayer insulating film IL1 does notcover the entire memory cell MC, and the upper surface of the memorygate electrode MG, the upper surface of the control gate electrode CG,the upper portion of the gate insulating film GF1, and the upper portionof the gate insulating film GF2 are exposed from the interlayerinsulating film IL1.

An opening CH3 and an opening CH4 are formed in the laminated filmincluding the interlayer insulating film IL1. The plug PG1 connected tothe diffusion region MD is filled inside the opening CH3, and the plugPG2 connected to the diffusion region MS is filled inside the openingCH4.

An interlayer insulating film IL2 is formed on the memory cell MC andthe interlayer insulating film IL1, and a plurality of plugs PG3 areformed in the interlayer insulating film IL2. Although not illustrated,a wiring served as a bit line, a wiring served as a source line, awiring for supplying an electric potential to the memory gate electrodeMG, a wiring for supplying an electric potential to the control gateelectrode CG, and the like are formed over the interlayer insulatingfilm IL2. The plug PG1 is electrically connected to a wiring served as abit line via the plug PG3, and the plug PG2 is electrically connected toa wiring served as a source line via the plug PG3. Although not shownhere, the memory gate electrode MG and the control gate electrode CG arealso connected to the above-mentioned wiring through the plug PG3. Thesewirings have a structure in which a conductive film mainly made ofcopper is filled in a trench for wiring, and are wirings having aso-called Damascene structure.

Operations of the Nonvolatile Memory

Next, an operation example of the nonvolatile memory cell will bedescribed with reference to FIGS. 5 and 6.

FIG. 5 shows an example of a nonvolatile memory module, and is anequivalent circuit diagram showing a connection relationship of fourmemory cells MC out of a plurality of memory cells MC. Each control gateelectrode CG is electrically connected to a driver for a control gateelectrode CG, each memory gate electrode MG is electrically connected toa driver for a memory gate electrode MG, each diffusion region MS as asource region is electrically connected to a driver for a source line,and each diffusion region MD as a drain region is electrically connectedto a decoder for a bit line.

FIG. 6 is a table showing an example of application conditions ofvoltages to the respective portions of the selected memory cell MCaamong the four memory cells MC shown in FIG. 5 at the time of “write”,“erase” and “read”. In the table of FIG. 6, in each time of “write”,“erase”, and “read”, a voltage Vd applied to the diffusion region MD,which is a drain region, a voltage Vcg applied to the control gateelectrode CG, a voltage Vmg applied to the memory gate electrode MG, avoltage Vs applied to the diffusion region MS, which is a source region,and a voltage Vb applied to the well region PW are described.

Note that what is shown in the table of FIG. 6 is a suitable example ofthe voltage application condition, and is not limited to this, and canbe variously changed as necessary. In the present embodiment, injectionof electrons into the charge storage layer CSL is defined as “writing”,and injection of holes into the charge storage layer CSL is defined as“erasing”.

The write operation is performed by a write method using hot electroninjection by source side injection, which is referred to as a SourceSide Injection (Source Side Injection) method. For example, a voltage asshown in the column of “write” in FIG. 6 is applied to each portion ofthe selected memory cell MCa to be written, and electrons are injectedinto the charge storage layer CSL of the selected memory cell MCa to bewritten.

At this time, hot electrons are generated in a channel region of the finFA covered with the memory gate electrode MG and the control gateelectrode CG, and hot electrons are injected into the charge storagelayer CSL under the memory gate electrode MG. The injected hot electronsare captured by the trap level in the charge storage layer CSL, and as aresult, the threshold voltage of the memory transistor having the memorygate electrode MG rises. That is, the memory transistor is in the writestate.

The erase operation is performed by an erase method using hot holeinjections by BTBT, which is called a BTBT (Band to Band Tunneling)method. That is, holes generated by BTBT in the diffusion region MS areinjected into the charge storage layer CSL to erase the charge storagelayer CSL. For example, voltages as shown in the column of “erase” inFIG. 6 are applied to respective portions of the selected memory cellMCa to be erased, holes are generated by BTBT phenomena, and holes areinjected into the charge storage layer CSL of the selected memory cellMCa by electric field acceleration. As a result, the threshold voltageof the memory transistor is lowered. That is, the memory transistor isin the erased state.

In the read operation, for example, a voltage as shown in the column of“read” in FIG. 6 is applied to each portion of the selected memory cellMCa to be read. By setting the voltage Vmg applied to the memory gateelectrode MG at the time of reading to a value between the thresholdvoltage of the memory transistor in the write state and the thresholdvoltage of the memory transistor in the erase state, it is possible todiscriminate between the write state and the erase state.

A Method of Manufacturing a Semiconductor Device

Hereinafter, a method of manufacturing a semiconductor device accordingto the present embodiment will be described with reference to FIGS. 7 to27. FIG. 7 is a plan view of a region in which a plurality of fins FAare formed, FIGS. 8 to 12 are cross-sectional views taken along line E-Eof FIG. 7, FIGS. 13 to 15, FIGS. 17 to 19, and FIGS. 21 to 27 arecross-sectional views taken along line A-A and line B-B of FIG. 1, andFIG. 16 is a cross-sectional view taken along line D-D of FIG. 1. FIG.20 is a perspective view corresponding to FIG. 19.

Hereinafter, a manufacturing process of the fin FA will be describedwith reference to FIGS. 7 to 12.

FIG. 7 shows a planar pattern of the resist pattern RP1 and theconductive film CF1, and shows a state in which a plurality of openingsCH1 are formed in the conductive film CF1. FIGS. 8 to 12 arecross-sectional views taken along the line E-E of FIG. 7, but also alongthe direction Y of FIG. 1.

First, as shown in FIG. 8, a semiconductor substrate SB made of p-typemonocrystalline silicon or the like having a resistivity of, forexample, about 1 to 10 Ω cm is prepared. Next, an insulating film SO1,an insulating film SN1, and a conductive film CF1 are formed in thisorder on the upper surface of the semiconductor substrate SB. Theinsulating film SO1 is made of, for example, silicon oxide, and can beformed by, for example, a thermal oxidation method or a CVD (ChemicalVapor Deposition) method. The thickness of the insulating film SO1 isabout 5 to 10 nm. The insulating film SN1 is made of, for example,silicon nitride, and is formed by, for example, a CVD method. Thethickness of the insulating film SN1 is about 20 to 100 nm. Theconductive film CF1 is made of, for example, amorphous carbon, and isformed by, for example, a CVD method. The thickness of the conductivefilm CF1 is about 20 to 200 nm.

Next, a resist pattern RP1 is formed on the conductive film CF1, and dryetching is performed by using the resist pattern RP1 as a mask to removea part of the conductive film CF1 exposed from the resist pattern RP1.As a result, a plurality of openings CH1 having substantially the samepattern as the resist pattern RP1 are formed in the conductive film CF1,and a part of the insulating film SN1 is exposed from the conductivefilm CF1. Thereafter, the resist pattern RP1 is removed by ashing or thelike.

FIG. 9 shows a step of forming the insulating film SN2.

An insulating film SN2 made of, e.g., silicon nitride is formed on theupper surface and the side surface of the conductive film CF1 and on theupper surface of the insulating film SN1 exposed at the bottom of theopening CH1 by, e.g., CVD. The thickness of the insulating film SN2 isabout 20 to 40 nm. Next, anisotropic etching is performed on theinsulating film SN2 to leave the insulating film SN2 on the side surfaceof the conductive film CF1 in the opening CH1. That is, the spacer-likeinsulating film SN2 is formed on the side surface of the conductive filmCF1 in a self-aligned manner.

FIG. 10 shows a step of removing the conductive film CF1.

The conductive film CF1 is removed by dry etching and wet etching underconditions in which the insulating films SN1 and SN2 are difficult to beetched.

FIG. 11 shows a process of forming the fin FA.

By performing anisotropic dry etching using the insulating film SN2 as amask, the insulating film SN1, the insulating film SO1, and a part ofthe semiconductor substrate SB are sequentially removed. As a result, afin FA which is a part of the semiconductor substrate SB and protrudesfrom the semiconductor substrate SB is formed immediately below theinsulating film SN2. In the present embodiment, the height of the fin FAis about 150 to 250 nm, and the width of the fin FA is about 20 to 40nm.

As described above, in the present embodiment, the insulating film SN2served as a mask for forming the fin FA is formed on the side surface ofthe conductive film CF1 in the opening CH1 in a self-aligned manner.Therefore, the insulating film SN2 does not become an isolated pattern,and is not easily collapsed. Further, although the width of the fin FAis determined by the width of the insulating film SN2, since the widthof the insulating film SN2 can be easily adjusted by changing theconditions of the anisotropic dry etching process, the method ofmanufacturing of the present embodiment is suitable for miniaturizationof the fin FA.

For example, in the case where the opening CH1 is not provided in theconductive film CF1 and the insulating film SN2 is formed on theinsulating film SN1 by patterning using a resist pattern, the insulatingfilm SN2 tends to collapse. Further, since the width of the fin FAdepends on the resolution of the resist pattern, such a method is notsuitable for miniaturization of the fin FA.

FIG. 12 shows a step of forming the insulating film SO2.

An insulating film SO2 made of, for example, silicon oxide or the likeis deposited by, for example, CVD so as to fill the space between theplurality of fins FA and cover the insulating film SN2.

Hereinafter, the manufacturing process subsequent to FIG. 12 will bedescribed with reference to FIGS. 13 to 27. FIG. 13 shows a step offorming the element isolation portion STI and the well PW, and a step ofremoving the insulating film SN2.

First, the upper surface of the insulating film SO2 is polished by a CMPmethod. At this time, the insulating film SN2 functions as an etchingstopper film for the polishing process. Next, wet etching is performedon the insulating film SO2, whereby the upper surface of the insulatingfilm SO2 is retracted to expose a part of the side surface of the finFA. The receded insulating film SO2 is served as an element isolationportion STI.

Next, wet etching is performed to remove the insulating film SN2. Theinsulating film SO1 and the insulating film SN1 are left on the uppersurface of the fin FA.

Next, a p-type well region PW is formed in the semiconductor substrateSB including the fin FA by introducing an impurity into thesemiconductor substrate SB including the fin FA by using aphotolithography method and an ion implantation method. The impurity forforming the p-type well regions PW is, for example, boron (B) or borondifluoride (BF₂). The well region PW is formed to extend over the entirefin FA and a part of the semiconductor substrate SB.

In this embodiment, although the diffusion region MD and the diffusionregion MS are formed by using the insulating film SO3 in a later step,an n-type impurity may be introduced into a part of the fin FA in whichthe diffusion region MD and the diffusion region MS are to be formed byusing a photolithography method and an ion implantation method after thestep of forming the well region PW. The region into which such animpurity is introduced can be used as a part of the diffusion region MDand a part of the diffusion region MS.

FIG. 14 shows a step of forming the insulating film SO03 and theinterlayer insulating film IL1.

First, an insulating film SO3 is formed on the insulating film SN1, theside surface of the fin FA, and the element isolation portion STI by,e.g., CVD. The insulating film SO03 is a silicon oxide film into whichan n-type impurity such as phosphorus (P) is introduced, and has athickness of about 20 nm. Next, an interlayer insulating film IL1 madeof, e.g., silicon oxide is formed on the insulating film SO3 by, e.g.,CVD. The thickness of the interlayer insulating film IL1 is about 400nm. Next, the upper surface of the interlayer insulating film IL1 isplanarized by the CMP method.

FIG. 15 shows a step of forming the opening CH2.

The interlayer insulating film IL1 and the insulating film SO03 areselectively patterned by a photolithography method and a dry etchingprocess, whereby openings CH2 are formed in the interlayer insulatingfilm IL1 and the insulating film SO3. As shown in the A-A cross section,the insulating film SO1 and the insulating film SN1 are left on theupper surface of the fin FA inside the openings CH2, but as shown in theB-B cross section, the side surface of the fin FA and the upper surfaceof the element isolation portion STI are exposed in the openings CH2.That is, the openings CH2 extends in the Y direction shown in FIG. 1,and is formed to open a part of the fin FA and a part of the elementisolation portion STI. Inside the openings CH2, a memory gate electrodeMG, a control gate electrode CG, a gate insulating film GF1, and a gateinsulating film GF2 are formed in a later step. The fin FA located atthe bottom of the openings CH2 is served as a channel region of thememory cell MC.

FIG. 16 shows a manufacturing process subsequent to FIG. 15, and shows across section along the line D-D of FIG. 1, and shows a process offorming the diffusion region MD.

In the D-D cross section, the insulating film SO03 is formed so as to bein contact with the side surface of the fin FA. In this state, byperforming heat treatment at about 800 to 950° C., the n-type impurityincluded in the insulating film SO3 is diffused into the fin FA andactivated. A diffusion region MD is formed in the fin FA by the diffusedn-type impurity. Although not shown, diffusion regions MS are alsoformed in the fins FA in this step.

In the present embodiment, the diffusion region MD and the diffusionregion MS are formed in a self-aligned manner with respect to theopenings CH2. In other words, the diffusion region MD and the diffusionregion MS are formed in the fin FA that is not opened by the openingsCH2.

FIG. 17 shows a process of forming the insulating film SO4, theconductive film FD, the dummy member D1, and the dummy member D2.

First, an insulating film SO4 made of silicon oxide is formed on theside surface of the fin FA exposed in the B-B cross section by a thermaloxidation method. Next, a conductive film FD such as a polycrystallinesilicon film is deposited on the interlayer insulating film IL1 and theinsulating film SN1 by, e.g., CVD so as to fill the openings CH2. Next,anisotropic etching is performed on the conductive film FD to remove theconductive film FD on the interlayer insulating film IL1, and aspacer-shaped dummy material D1 and a dummy material D2 are formed inthe openings CH2 in a self-aligned manner. That is, inside openings CH2,a dummy material D1 is formed on the first side of the interlayerinsulating film IL1, and a dummy material D2 is formed on the secondside of the interlayer insulating film IL1 facing the first side. Thewidths of the spacer-shaped dummy material D1 and the dummy material D2in the A-A cross section are about 30 to 40 nm, respectively. Althoughnot shown here, the dummy material D1 and the dummy material D2 areformed of the same conductive film FD and are integrated at the end ofthe memory cell MC.

As shown in FIG. 17, the dummy material D1 and the dummy material D2 areformed to be separated from each other in one opening CH2. Here,although not shown, an insulating film SO4 is formed on the side surfaceof the fin FA located between the dummy material D1 and the dummymaterial D2. Therefore, during the anisotropic etching process for thepolycrystalline silicon film, the fin FA made of silicon is protected bythe insulating film SO4. Therefore, it is possible to prevent the fin FAlocated between the dummy material D1 and the dummy material D2 frombeing scraped.

FIG. 18 shows a step of forming the insulating film SN3 and the dummymaterial D3.

An insulating film SN3 made of, for example, silicon nitride is formedby, for example, CVD so as to cover the dummy material D1 and the dummymaterial D2 inside the openings CH2. The thickness of the insulatingfilm SN3 is about 2 to 3 nm. Next, a dummy material D3 made of aconductive film such as a polycrystalline silicon film is deposited onthe insulating film SN3 by, e.g., CVD. The dummy material D3 is formedin a self-aligned manner so as to fill a space between the dummymaterial D1 and the dummy material D2 adjacent to each other in theopenings CH2. The material of the dummy material D3 may be anothermaterial different from the polycrystalline silicon film. However, thedummy material D3 is removed by etching together with the dummy materialD1 or the dummy material D2 in a later step. Therefore, in order toavoid complication of the etching process, the material of the dummymaterial D3 is preferably the same as that of the dummy material D1 andthe dummy material D2.

FIG. 19 shows a polishing process for the insulating film SN3, theinterlayer insulating film IL1, the dummy material D1, the dummymaterial D2, and the dummy material D3.

The insulating film SN3, the interlayer insulating film IL1, the dummymaterial D1, the dummy material D2, and the dummy material D3 arepolished by the CMP method. This lowers these heights. The dummymaterial D1, the dummy material D2, the dummy material D3, and theinsulating film SN3 thus formed in the openings CH2 constitute a part ofthe dummy pattern DP.

FIG. 20 is a perspective view at the time when the manufacturing processof FIG. 19 is completed.

Here, some of the features of the present embodiment will be described.As shown in FIG. 20, a dummy pattern DP is filled inside the holes CH2.The dummy pattern DP is a pattern for replacing the memory gateelectrode MG, the control gate electrode CG, and the like in a laterstep. One of the features of the present embodiment is that the dummymaterial D1, the dummy material D2, and the dummy material D3, which arepart of the dummy pattern DP, are formed in a self-aligned manner.

Hereinafter, as a comparative example for the features of the presentembodiment, the techniques disclosed in Patent Document 2 (JapaneseUnexamined Patent Application Publication No. 2017-45860) and PatentDocument 3 (Japanese Unexamined Patent Application Publication No.2014-127527) described above will be described.

Referring to the technique of forming the MONOS transistor as afin-structure transistor as described in the above-mentioned document 2,first, a control gate electrode CG is formed by patterning so as tocover the upper surface and the side surface of the fin FA, and then apolycrystalline film is formed so as to cover the control gate electrodeCG. Next, anisotropic etching is performed on the polycrystallinesilicon film to form a memory gate electrode MG in the shape of asidewall spacer on the side surface of the control gate electrode CG.

However, in the fin structure transistor, when patterning the controlgate electrode CG, an etching process having a high aspect ratio isrequired depending on the height of the fin FA. During processing of thememory gate electrode MG, the memory gate electrode MG is formed notonly on the side surface of the control gate electrode CG but also onthe side surface of the fin FA. The memory gate electrode MG formed onthe side surface of the fin FA may cause a short circuit betweenadjacent memory cells MC, and needs to be removed. Therefore, inconsideration of the height of the fin FA, it is necessary to performthe anisotropic etching process in overetching at the time of processingthe memory gate electrode MG. In this case, since the etching isperformed in a state where the upper surface of the control gateelectrode CG is exposed, it is necessary to form a cap film having anetching selectivity on the control gate electrode CG or to make thethickness of the control gate electrode CG sufficiently thick.

Therefore, the height of the control gate electrode CG increases, andthe aspect ratio at the time of patterning the control gate electrode CGbecomes very high. In particular, as the miniaturization of thesemiconductor element progresses, the control gate electrode CG having afine gate length and a large thickness exists as an isolated elongatedpattern. In this case, the control gate electrode CG may collapse, andthe yield of the semiconductor device may be lowered.

On the other hand, there is a technique of replacing a dummy patternwith a control gate electrode CG made of a metal film or the like by aso-called gate last process as described in Patent Document 3. However,the dummy pattern is formed by patterning a polycrystalline silicon filmor the like. Therefore, when the technique of Patent Document 3 isapplied to a transistor having a fin structure, it is necessary toincrease the height of the dummy pattern and form the memory gateelectrode MG on the side surface of the dummy pattern by anisotropicetching. That is, also in Patent Document 3, the same problem as inPatent Document 2 occurs, and there is a possibility that the dummypattern collapses.

In contrast to these techniques, in the present embodiment, as describedwith reference to FIGS. 15 to 19, the openings CH2 is formed in theinterlayer insulating film IL1, and the dummy material D1, the dummymaterial D2, and the dummy material D3 are formed in self-alignment inthe openings CH2. That is, in the openings CH2, the dummy material D1and the dummy material D2 are formed along the side surface of theinterlayer insulating film IL1, and the dummy material D3 is formedalong the side surface of the dummy material D1 and the dummy materialD2 via the insulating film SN3. Therefore, it is possible to suppressthe possibility that the dummy material D1, the dummy material D2, andthe dummy material D3 collapse. As described above, according to thepresent embodiment, it is possible to improve the yield in themanufacturing process of the semiconductor device.

Further, the gate length of the control gate electrode CG, the gatelength of the memory gate electrode MG, the thickness of the gateinsulating film GF1, and the thickness of the gate insulating film GF2mainly depend on the diameter of the openings CH2, and can be easilyadjusted by the conditions of the anisotropic etching process forprocessing the dummy material D1 and the dummy material D2. Therefore,miniaturization of the memory cell MC can be promoted.

Hereinafter, a manufacturing process of replacing the region where thedummy pattern DP is formed with the control gate electrode CG, thememory gate electrode MG, the gate insulating film GF1, and the gateinsulating film GF2 will be described.

FIG. 21 shows a step of removing the dummy material D1.

First, a resist pattern RP2 having a pattern for opening a dummymaterial D1, which is a part of the dummy pattern DP, is formed on theinterlayer insulating film IL1. Next, dry etching and wet etching areperformed by using the resist pattern RP2 as a mask to remove the dummymaterial D1 formed in the openings CH2. At this time, as shown in theB-B cross section, since the insulating film SO4 formed on the sidesurface of the fin FA are served as a protective film against theetching process, it is possible to prevent the fin FA from being shaved.

FIG. 22 shows a step of removing the insulating film SO4, the insulatingfilm SO1, and the insulating film SN1.

The insulating film SO1, the insulating film SN1, and the insulatingfilm SO4 exposed by removing the dummy material D1 are removed by dryetching and wet etching using the resist pattern RP2 as a mask. As aresult, the upper surface and the side surface of the fin FA not coveredwith the interlayer insulating film IL1 are exposed as shown in the B-Bcross section.

Further, after these steps, an isotropic etching process such as a wetetching process may be further performed to cause a part of the sidesurfaces of the interlayer insulating film IL1, the insulating film SO3,the insulating film SN1, and the insulating film SO01 in the openingsCH2 to recede. By performing such processing, the position of the endportion of the diffusion region MS and the end portion of the memorygate electrode MG to be formed later can be adjusted. FIG. 22 shows astate in which each insulating film such as the interlayer insulatingfilm IL1 in the openings CH2 is retracted. Thereafter, the resistpattern RP2 is removed by ashing or the like.

FIG. 23 shows a step of forming the gate insulating film GF1 and thememory gate electrode MG.

First, in the openings CH2, an insulating film X1 made of, for example,silicon oxide is formed on the side surface of the insulating film SN3,the upper surface and the side surface of the interlayer insulating filmIL1, and the upper surface and the side surface of the fin FA by, forexample, CVD. Next, a charge storage layer CSL made of, e.g., siliconnitride is formed on the insulating film X1 by, e.g., CVD. Instead ofthe silicon nitride film, the charge storage layer CSL may be a metaloxide film such as a hafnium silicate (HfSiO) film. Next, an insulatingfilm X2 made of, e.g., silicon oxide is formed on the charge storagelayer CSL by, e.g., CVD. The insulating film X2 may be a metal oxidefilm such as an alumina film, for example, instead of a silicon oxidefilm. The insulating film X1, the charge storage layer CSL, and theinsulating film X2 are served as a gate insulating film GF1.

In the present embodiment, the insulating film X1, the charge storagelayer CSL, and the insulating film X2 are not shown in detail for thesake of clarity, and these laminated films are shown as the gateinsulating film GF1.

Next, a memory gate electrode MG made of, for example, polycrystallinesilicon into which an n-type impurity is introduced is formed on thegate insulating film GF1 by, for example, a CVD method. Instead of thepolycrystalline silicon film, the memory gate electrode MG may be atantalum nitride film, a single-layer metal film made of an aluminumfilm, or a laminated film in which these films are appropriatelystacked.

Next, the memory gate electrode MG and the gate insulating film GF1formed on the upper surface of the interlayer insulating film IL1 areremoved by the CMP method. As a result, in the openings CH2, the gateinsulating film GF1 and the memory gate electrode MG are filled in theregion where the dummy material D1, which is a part of the dummy patternDP, is removed.

FIG. 24 shows a step of removing the dummy material D2, the dummymaterial D3, the insulating film SN3, the insulating film SO1, theinsulating film SN1, and the insulating film SO4.

First, a resist pattern RP3 having a pattern for opening the dummymaterial D2, the dummy material D3, and the insulating film SN3, whichare the dummy patterns DP left in the openings CH2, is formed on theinterlayer insulating film IL1. Next, dry etching and wet etching areperformed by using the resist pattern RP3 as a mask to remove the dummymaterial D2, the dummy material D3, and the insulating film SN3remaining in the openings CH2. The insulating film SN3 in contact withthe gate insulating film GF1 in the openings CH2 may not be removed ormay be left. When the insulating film SN3 is left, the dielectricstrength between the memory gate electrode MG and the control gateelectrode CG, which will be described later, can be improved.

Further, although not shown here, similarly to the process of FIG. 21,since the insulating film SO4 formed on the side surface of the fin FAis served as a protective film against the etching process, it ispossible to prevent the fin FA from being shaved.

Next, the insulating film SO1, the insulating film SN1, and theinsulating film SO4 exposed by removing the dummy material D2, the dummymaterial D3, and the insulating film SN3 are removed by dry etching andwet etching using the resist pattern RP3 as a mask. As a result, theupper surface and the side surface of the fin FA are exposed.

Further, after these steps, an isotropic etching process such as a wetetching process may be further performed to cause a part of the sidesurfaces of the interlayer insulating film IL1, the insulating filmSO03, the insulating film SN1, and the insulating film SO01 in theopenings CH2 to recede. By performing such processing, the position ofthe end portion of the diffusion region MD and the end portion of thecontrol gate electrode CG to be formed later can be adjusted.Thereafter, the resist pattern RP3 is removed by ashing or the like.

FIG. 25 shows a step of forming the gate insulating film GF2 and thecontrol gate electrode CG.

First, inside the openings CH2, a metal oxide film such as a hafniumoxide film (HfO film) is formed on the side surface of the gateinsulating film GF1, the upper surface and the side surface of theinterlayer insulating film IL1, and the upper surface and the sidesurface of the fin FA by, e.g., CVD.

Next, a control gate electrode CG is formed on the gate insulating filmGF2 by a sputtering method or a CVD method by using a tantalum nitridefilm, a single-layer metal film made of an aluminum film, or a laminatedfilm of these films as appropriate.

Next, the control gate electrode CG and the gate insulating film GF2formed on the upper surface of the interlayer insulating film IL1 areremoved by the CMP method. Thus, the gate insulating film GF2 and thecontrol gate electrode CG are filled inside the hole CH2.

Before forming the gate insulating film GF2 and the control gateelectrode CG, an insulating film such as a silicon oxide film may beformed in the openings CH2, and an anisotropic etching process may beperformed on the insulating film to leave a spacer-shaped insulatingfilm on the side surface of the gate insulating film GF1. When thespacer-shaped insulating film is formed, the dielectric strength betweenthe memory gate electrode MG and the control gate electrode CG can beimproved.

As described above, the process of replacing the dummy material D1, thedummy material D2, the dummy material D3, and the insulating film SN3,which are the dummy patterns DP formed in the openings CH2, with thecontrol gate electrode CG, the memory gate electrode MG, the gateinsulating film GF1, and the gate insulating film GF2 is completed.

In the present embodiment, the memory gate electrode MG and the gateinsulating film GF1 are formed first, and then the control gateelectrode CG and the gate insulating film GF2 are formed, but this ordermay be reversed. However, if the gate insulating film GF2 is thin andthe influence of the thermal history is large, the threshold voltage ofthe control transistor is liable to vary. When the gate insulating filmGF2 is formed first, the insulating film X1, the charge storage layerCSL, and the insulating film X2 are sequentially formed in thesubsequent step of forming the gate insulating film GF1, and thus thethermal history increases. Therefore, it is preferable to form thememory gate electrode MG and the gate insulating film GF1 first.

FIG. 26 shows a step of forming the openings CH3 and CH4.

First, a resist pattern RP4 having a pattern in which the diffusionregion MD and the diffusion region MS are opened is formed on theinterlayer insulating film IL1. Next, dry etching is performed by usingthe resist pattern RP4 as a mask to form a openings CH3 reaching thediffusion region MD and openings CH4 reaching the diffusion region MS inthe interlayer insulating film IL1, the insulating film SO3, theinsulating film SN1, and the insulating film SO1. Thereafter, the resistpattern RP4 is removed by ashing or the like.

FIG. 27 shows a process of forming the plug PG1 and the plug PG2.

First, a barrier metal film made of, for example, titanium nitride isformed inside the openings CH3, and inside the openings CH4, and on theinterlayer insulating film IL1 by, for example, a sputtering method.Next, a conductive film made of, e.g., tungsten is formed on the barriermetal film by, e.g., CVD. Next, the barrier metal film and theconductive film formed on the interlayer insulating film IL1 are removedby the CMP method. As a result, the plug PG1 and the plug PG2 includingthe barrier metal film and the conductive film are formed in theopenings CH3 and the openings CH4, respectively.

In addition, the upper surfaces of the interlayer insulating film IL1,the memory gate electrode MG, the control gate electrode CG, the gateinsulating film GF1, and the gate insulating film GF2 are polished bythe polishing process by using the CMP method, and the positions of theupper surfaces thereof are lowered.

Following the manufacturing process of FIG. 27, the interlayerinsulating film IL2 and the plug PG3 are formed, whereby thesemiconductor device shown in FIGS. 3 and 4 is manufactured.

First, an interlayer insulating film IL2 made of, e.g., silicon oxide isformed on the interlayer insulating film IL1, the control gate electrodeCG, the memory gate electrode MG, the plug PG1, and the plug PG2 by,e.g., CVD. Next, a contact hole is formed in the interlayer insulatingfilm IL2, and a barrier metal film made of titanium nitride, aconductive film made of tungsten, and the like are filled inside thecontact hole, thereby forming a plug PG3. Although not shown here, theplug PG3 is also formed on the control gate electrode CG and the memorygate electrode MG by this step.

First Modified Example

Hereinafter, a semiconductor device of first modified example of thefirst embodiment will be described with reference to FIGS. 28 to 31. Inthe following description, differences from the first embodiment will bemainly described.

In the first embodiment, the manufacturing process of the fin FA hasbeen described with reference to FIGS. 7 to 11, but in the firstmodified example, the other manufacturing process of the fin FA will bedescribed.

FIGS. 28 to 31 correspond to the cross-sectional view taken along theline E-E of FIG. 7, and are also cross-sectional views taken along thedirection Y of FIG. 1.

First, as shown in FIG. 28, similarly to the first embodiment, asemiconductor substrate SB is prepared, an insulating film SO1 is formedon the semiconductor substrate SB, and an insulating film SN1 is formedon the insulating film SO1. Next, an insulating film SO06 made of, e.g.,silicon oxide is formed on the insulating film SN1 by, e.g., CVD. Thethickness of the insulating film SO06 is about 20 to 200 nm. Next, aresist pattern RP5 is formed on the insulating film SO6, and dry etchingis performed by using the resist pattern RP5 as a mask to remove a partof the insulating film SO6 exposed from the resist pattern RP5. As aresult, a plurality of openings CH5 are formed in the insulating filmSO6, and a part of the insulating film SN1 is exposed from theinsulating film SO6. Thereafter, the resist pattern RP5 is removed byashing or the like.

FIG. 29 shows a step of forming the conductive film CF2.

First, a conductive film CF2 made of, for example, amorphous carbon isformed on the upper surface and the side surface of the insulating filmSO6 and on the upper surface of the insulating film SN1 exposed at thebottom of the openings CH5 by, for example, CVD. The thickness of theconductive film CF2 is about 20 to 40 nm. Next, anisotropic etching isperformed on the conductive film CF2 to leave the conductive film CF2 onthe side surface of the insulating film SO6 in the openings CH5. Thatis, the spacer-shaped conductive film CF2 can be formed on the sidesurface of the insulating film SO6 in a self-aligned manner.

FIG. 30 shows a step of forming the insulating film SO07.

First, an insulating film SO07 made of, for example, silicon oxide isformed by, for example, CVD so as to fill the openings CH5 and cover theinsulating film SO6 and the conductive film CF2. Next, by polishing theinsulating film SO7 by the CMP method, the conductive film CF2 and theinsulating film SO7 are left in the openings CH5, and the insulatingfilm SO7 formed on the upper surface of the insulating film SO6 and onthe upper surface of the conductive film CF2 is removed. That is, theconductive film CF2 and the insulating film SO07 are buried in theopenings CH5. As described above, the insulating film SO7 can be formedbetween the two conductive films CF2 in a self-aligned manner. Inaddition, the upper surfaces of the insulating film SO06, the conductivefilm CF2, and the insulating film SO07 are slightly removed by thispolishing treatment.

FIG. 31 shows a step of removing the conductive film CF2 and a step offorming the fin FA.

First, anisotropic dry etching is performed by using the insulatingfilms SO6 and SO07 as masks to remove the conductive film CF2. Next,anisotropic dry etching is continued, whereby the insulating film SN1,the insulating film SO01, and a part of the semiconductor substrate SBare sequentially removed. As a result, a fin FA which is a part of thesemiconductor substrate SB and protrudes from the semiconductorsubstrate SB is formed immediately under the insulating films SO6 andSO07.

The subsequent manufacturing process is the same as the manufacturingprocess from FIG. 12 onward in the first embodiment.

As described above, in the first modified example, the conductive filmCF2 is formed on the side surface of the insulating film SO6 in theopenings CH5 in a self-aligned manner, and the insulating film SO07 isformed on the side surface of the conductive film CF2 in a self-alignedmanner. Therefore, it is difficult for the conductive film CF2 and theinsulating film S07 to collapse. In the region where the conductive filmCF2 is removed, the fin FA is formed by using the insulating film SO6and the insulating film SO7 as a mask. Therefore, the fin FA can bestably formed in the same manner as in the first embodiment.

Second Modified Example

Hereinafter, a semiconductor device of second modified example of thefirst embodiment will be described with reference to FIG. 32. In thefollowing description, differences from the first embodiment will bemainly described.

In the first embodiment, the main part of the memory cell MC is mainlydescribed, but in the second modified example the structure around theend part of the memory cell MC is described.

FIG. 32 is a plan view at the time when the manufacturing process ofFIGS. 19 and 20 is completed, and a region indicated by a dashed line isan open region OP1 of the resist pattern RP2 formed in FIG. 21. Asdescribed in the first embodiment, the dummy material D1 and the dummymaterial D2 are formed of the same conductive film FD, and areintegrated at the end portion of the memory cell MC.

In the second modified example, as shown in FIG. 32, one end of theopening region OP1 is located on the interlayer insulating film IL1, andthe other end of the opening region OP1 is located on the dummy materialD1. In this state, when the dry etching process is performed on thedummy material D1, a part of the dummy material D1 is left on the sidesurface of the insulating film SN3 in the openings CH2, and thereafter,as the isotropic etching process, for example, the wet etching processis performed to remove the remaining dummy material D1. By forming theinsulating film SN3 with a film which is difficult to be cut by theisotropic etching process, the dummy material D3 is not cut even if theisotropic etching process is performed by overetching. That is, thedummy material D1 can be removed by performing the isotropic etchingprocess and using the insulating film SN3 between the dummy material D1and the dummy material D3 as the etching stopper film.

In this manner, the dummy material D1 can be removed even if the openingregion OP1 of the resist pattern RP2 does not have the entire opening ofthe dummy material D1 in the X direction. Therefore, a margin can beprovided for the misalignment of the resist pattern RP2.

The technique disclosed in the second modified example can also beapplied to the first modified example described above.

Third Modified Example

Hereinafter, a semiconductor device according to a third modifiedexample of the first embodiment will be described with reference to FIG.33. In the following description, differences from the above-describedsecond modified example will be mainly described.

In the third modified example, the opening region OP2 which is a patternobtained by changing the opening region OP1 of the second modifiedexample will be described.

FIG. 33 is a plan view at the time when the manufacturing process ofFIGS. 19 and 20 is completed, and a region indicated by a dashed line isan open region OP2 of the resist pattern RP2 formed in FIG. 21.

In the third modified example, as shown in FIG. 33, one end of theopening region OP2 is located on the interlayer insulating film IL1, andthe other end of the opening region OP2 is located on the dummy materialD3. By performing dry etching in this state, the dummy material D1 andthe dummy material D3 can be removed. Further, since the insulating filmSN3 between the dummy material D1 and the dummy material D3 has a smallthickness, the insulating film SN3 can also be removed by dry etching ofthe dummy material D1 and the dummy material D3.

In addition, a part of the dummy material D3 may be left in the dryetching process. Therefore, the remaining dummy material D3 can beremoved by performing, for example, a wet etching process as theisotropic etching process. By forming the insulating film SN3 with afilm which is difficult to be cut by the isotropic etching process, thedummy material D2 is not cut even if the isotropic etching process isperformed by overetching. That is, the dummy material D3 can be removedby performing the isotropic etching process and using the insulatingfilm SN3 between the dummy material D2 and the dummy material D3 as theetching stopper film.

As described above, in either of the first modified example and thesecond modified example, a margin can be provided for the misalignmentof the resist pattern RP2. The opening region OP1 of the first modifiedexample and the opening region OP2 of the second modified example areregions in which the memory gate electrode MG and the gate insulatingfilm GF1 are formed in a later step. Therefore, by applying either thefirst modified example or the second modified example, it is possible toeasily change the design such as the gate length of the memory gateelectrode MG.

The technique disclosed in the third modified example can also beapplied to the first modified example described above.

Fourth Modified Example

Hereinafter, a semiconductor device of a fourth modified example of thefirst embodiment will be described with reference to FIGS. 34 and 35. Inthe following description, differences from the first embodiment will bemainly described.

In a fourth modified example as well, the structure around the endportion of the memory cell MC will be described in the same manner as inthe second modified example and the third modified example describedabove.

FIGS. 34 and 35 are plan views showing a manufacturing process addedbetween FIGS. 20 and 21. The region indicated by the dashed line in FIG.34 is the opening region OP3 of the resist pattern used in the fourthmodified example.

As shown in FIG. 34, the openings CH2 has a plurality of replacementregions RR and connection regions CR. The substitution region RR is thesame as the openings CH2 described in the first embodiment, and extendsin the Y direction. That is, the replacement region RR is a region inwhich the dummy pattern DP is removed and replaced with the memory gateelectrode MG, the control gate electrode CG, the gate insulating filmGF1, and the gate insulating film GF2 in a later step.

The connection region CR is a region that extends in the X direction andconnects the plurality of replacement regions RR at the end of thememory cell MC, and is a region that is integrated with the plurality ofreplacement regions RR. Although the dummy pattern DP is embedded in theconnection region CR similarly to the replacement region RR, the dummypattern DP in the connection region CR is a region which is not replacedby the memory gate electrode MG, the control gate electrode CG, or thelike, but is replaced by the interlayer insulating film IL3.

FIG. 35 shows the manufacturing process following FIG. 34.

The dummy pattern DP in the connection region CR shown in FIG. 34 isremoved by dry etching and wet etching by using the resist patternhaving the opening region OP3 as a mask. Thereafter, the resist patternis removed by ashing or the like.

Next, an interlayer insulating film IL3 made of, e.g., silicon oxide isformed by, e.g., CVD so as to embed the connection region CR from whichthe dummy pattern DP has been removed and cover the replacement regionRR. Next, the interlayer insulating film IL3 outside the connectionregion CR is removed by the CMP method, so that the interlayerinsulating film IL3 is filled in the connection region CR.

As described above, the interlayer insulating film IL3 is formed in theconnection region CR, so that the replacement regions RR are physicallyseparated from each other. That is, in a later step, the memory gateelectrode MG and the control gate electrode CG of each memory cell MCcan be physically separated.

As in the first embodiment, the memory gate electrode MG and the gateinsulating film GF1 may be formed after the control gate electrode CGand the gate insulating film GF2 are formed first. The flash memoryperforms an operation of collectively writing (or reading) data to(from) a plurality of memory cells MC. At this time, since it isnecessary to simultaneously apply the same voltage to a plurality ofmemory gate electrodes MG, it is desirable to configure the memory gateelectrodes MG so as to be connected to other memory gate electrodes MGadjacent to each other at the end portion of the memory cell MC.

When the control gate electrode CG is formed first, in order to connectthe plurality of memory gate electrodes MG to each other, the memorygate electrode MG needs to be formed so as to pass over the control gateelectrode CG. Therefore, when patterning the memory gate electrode ofthe overlying portion, an etching process or the like is performed onthe control gate electrode CG. At this time, when the control gateelectrode CG is formed first, since the gate insulating film GF1 isformed on the control gate electrode CG, the patterning of the memorygate electrode MG can be performed using the gate insulating film GF1 asan etching stopper.

When the memory gate electrode MG is formed first, it is necessary topattern the control gate electrode CG on the memory gate electrode MG.At this time, a gate insulating film GF2 is formed on the memory gateelectrode MG. Since the thickness of the gate insulating film GF2 issmaller than that of the gate insulating film GF1 having the chargestorage layer CSL therein, the reliability of the gate insulating filmGF2 as an etching stopper is inferior to that of the gate insulatingfilm GF1. Therefore, when the memory gate electrode MG is formed first,the memory gate electrode MG can be formed more reliably.

The technique disclosed in the fourth modified example can also beapplied to the first to third modified example described above.

Fifth Modified Example

Hereinafter, a semiconductor device of the fifth modified example of thefirst embodiment will be described with reference to FIG. 36. In thefollowing description, differences from the above-described the fourthmodified example will be mainly described.

In the fifth modified example, the opening region OP4 which is a patternobtained by changing the opening region OP3 of the fourth modifiedexample will be described.

FIG. 36 is a plan view showing a manufacturing process added betweenFIG. 20 and FIG. 21. The region indicated by the dashed line in FIG. 36is the opening region OP4 of the resist pattern used in the fifthmodified example.

As shown in FIG. 36, similarly to the fourth modified example, theopenings CH2 has a plurality of substitution regions RR and connectionregions CR, but unlike the fourth modified example, the width of theconnection region CR of the fifth modified example is smaller than thewidth of the connection region CR of the fourth modified example in theY direction. In FIG. 36, the width of the replacement region RR in the Xdirection is indicated by W1, and the width of the connection region CRin the Y direction is indicated by W2. Here, the width W2 is smallerthan ½ of the width W1.

Therefore, only the dummy material D4 is filled in the connection regionCR. The dummy material D4 is a part of the dummy pattern DP, isintegrated with the dummy material D1 and the dummy material D2, and isformed of the same conductive film FD as the dummy material D1 and thedummy material D2. That is, since the width of the connection region CRis narrow, the conductive film FD formed in the connection region CR isprocessed by the anisotropic etching process in the step of FIG. 17, butis left as the dummy material D4 so as to fill the connection region CR.Therefore, in the steps of FIGS. 18 and 19, the insulating film SN3 andthe dummy material D3 are not formed in the connection region CR.

Thereafter, the dummy material D4 in the connection region CR isremoved, and the interlayer insulating film IL3 is filled in theconnection region CR in the same manner as in the fourth modifiedexample.

In the fourth modified example, a dummy material D1, a dummy materialD2, a dummy material D3, and an insulating film SN3 constituting thedummy pattern DP are formed in the connection region CR. In contrast, inthe fifth modified example, since only the dummy material D4 is formedin the connection region CR, the dummy material D4 can be easily removedby etching.

The technique disclosed in the fifth modified example can also beapplied to the first to third modified example described above.

Sixth Modified Example

Hereinafter, a semiconductor device of a sixth modified example of thefirst embodiment will be described with reference to FIG. 37. In thefollowing description, differences from the first embodiment will bemainly described.

In the sixth modified example, the power supply region MSR of the memorygate electrode MG and the power supply region CSR of the control gateelectrode CG will be described as the structure of the end portion ofthe memory cell MC.

FIG. 37 is a plan view at the time when the manufacturing process ofFIGS. 19 and 20 is completed, and a region indicated by a dashed line isan open region OP5 of the resist pattern RP2 formed in FIG. 21. Theregion indicated by the two-dot chain line is the opening region OP6 ofthe resist pattern RP3 formed in FIG. 24. In FIG. 37, the plug PG3connected to the memory gate electrode MG in the power supply region MSRand the plug PG3 connected to the control gate electrode CG in the powersupply region CSR are shown by broken lines for convenience.

As shown in FIG. 37, the openings CH2 has a substitution region RR, apower supply region MSR, and a power supply region CSR. The substitutionregion RR is the same as the openings CH2 described in the firstembodiment, and extends in the Y direction. That is, the replacementregion RR is a region in which the dummy material D1 which is the dummypatterns DP, the dummy material D2, the dummy material D3, and theinsulating film SN3, are removed in a later step, and is a region to bereplaced with the memory gate electrode MG, the control gate electrodeCG, the gate insulating film GF1, and the gate insulating film GF2.

The power supply region MSR extends in the Y direction at one endportion of the memory cell MC, is integrated with the replacement regionRR, and is a region in which the plug PG3 is formed in the memory gateelectrode MG in a later step.

The power supply region CSR extends in the Y direction at the other endof the memory cell MC and is integrated with the substitution region RR,and is a region in which a plug PG3 is formed in the control gateelectrode CG in a later step.

In the Y direction, the power supply region MSR and the power supplyregion CSR are formed at opposite ends of the memory cell MC. That is,in the Y direction, the plug PG3 formed in the power supply region MSRis formed on the opposite side of the plurality of fins FA to the plugPG3 formed in the power supply region CSR.

In FIG. 37, the width of the substitution region RR in the X directionis indicated by W1, and the width of the power supply region MSR and thewidth of the power supply region CSR in the X direction are indicated byW3, respectively. In other words, the width of the openings CH2 on theupper surface of the fin FA served as the main portion of the memorycell MC is W1, and the width of the openings CH2 in the region where theplug PG3 is formed in a later step is W3. Here, the width W3 is smallerthan ½ of the width W1.

Therefore, only the dummy material D5 is filled in the power supplyregion MSR, and only the dummy material D6 is filled in the power supplyregion CSR. The dummy material D5 and the dummy material D6 are part ofthe dummy pattern DP, are integrated with the dummy material D1 and thedummy material D2, and are formed of the same conductive film FD as thedummy material D1 and the dummy material D2. That is, since the width W3of the power supply region MSR and the power supply region CSR isnarrow, the conductive film FD formed in the power supply region MSR andthe power supply region CSR is processed by the anisotropic etchingprocess in the step of FIG. 17, but is left as the dummy material D5 andthe dummy material D6 so as to fill the inside of the power supplyregion MSR and the inside of the power supply region CSR, respectively.Therefore, in the steps of FIGS. 18 and 19, the insulating film SN3 andthe dummy material D3 are not formed in the power supply region MSR andthe power supply region CSR. Therefore, since only the dummy material D5and the dummy material D6 are formed in the power supply region MSR andthe power supply region CSR, respectively, it is easy to remove thedummy material D5 and the dummy material D6 by the etching process.

Hereinafter, the manufacturing process of the the sixth modified examplewill be described with reference to FIGS. 21, 23, 24, and 25 in additionto FIG. 37.

In the step of FIG. 21, the dummy material D1 and the dummy material D5as the dummy pattern DP are removed in the opening region OP5. In thestep of FIG. 23, the memory gate electrode MG and the gate insulatingfilm GF1 are formed in a region where the dummy pattern DP (the dummymaterial D1 and the dummy material D5) in the opening region OP5 isremoved. That is, a part of the replacement region RR and the dummypattern DP (dummy material D1 and dummy material D5) formed in the powersupply region MSR are replaced with the memory gate electrode MG and thegate insulating film GF1.

In addition, in the step of FIG. 24, in the opening region OP6, thedummy material D2, the dummy material D3, the dummy material D6, and theinsulating film SN3 which are the dummy patterns DP are removed. In thestep of FIG. 25, the control gate electrode CG and the gate insulatingfilm GF2 are formed in a region where the dummy pattern DP (the dummymaterial D2, the dummy material D3, the dummy material D6, and theinsulating film SN3) in the opening region OP6 is removed. That is, thedummy pattern DP (dummy material D2, dummy material D3, dummy materialD6, and insulating film SN3) left in the replacement region RR and thepower supply region CSR is replaced with the control gate electrode CGand the gate insulating film GF2.

Thereafter, as described in the manufacturing steps of FIGS. 3 and 4,the plug PG3 is formed on the memory gate electrode MG of the powersupply region MSR, and the plug PG3 is formed on the control gateelectrode CG of the power supply region CSR.

The technique disclosed in the sixth modified example can also beapplied to the first to third modified example described above.

Hereinafter, a semiconductor device of the second embodiment will bedescribed with reference to FIGS. 38 and 39. In the followingdescription, differences from the first embodiment will be mainlydescribed.

In the first embodiment, as described with reference to FIG. 16, thediffusion region MD and the diffusion region MS are formed in the fin FAby diffusing the impurity from the insulating film SO3 into which then-type impurity is introduced, which is formed between the fin FA andthe interlayer insulating film IL1, into the fin FA.

In the second embodiment, a diffusion region MD and a diffusion regionMS are formed in the fin FA by using another method.

FIGS. 38 and 39 are cross-sectional views taken along line A-A and lineD-D shown in FIG. 1. FIG. 38 shows a manufacturing process subsequent toFIG. 25 of the first embodiment. In the second embodiment, it is assumedthat the insulating film SO3 is not formed between the fin FA and theinterlayer insulating film IL1, and the heat treatment step of FIG. 16is omitted.

First, as shown in FIG. 38, the interlayer insulating film IL1, theinsulating film SN1, and the insulating film SO01 are removed by dryetching and wet etching. As a result, the upper surface and the sidesurface of the fin FA are exposed in the region where the memory gateelectrode MG, the control gate electrode CG, the gate insulating filmGF1, and the gate insulating film GF2 are not formed.

Next, as shown in FIG. 39, an insulating film SO05 into which an n-typeimpurity is introduced is formed by, e.g., CVD so as to be in contactwith the fin FA. Next, by performing heat treatment at about 800 to 950°C., the n-type impurity contained in the insulating film SO5 is diffusedinto the fin FA and activated. A diffusion region MD is formed in thefin FA by the diffused n-type impurity. Although not shown, thediffusion region MS is also formed in the same manner as the diffusionregion MD.

Thereafter, for example, a silicon oxide film is formed on theinsulating film SO05 by, e.g., CVD, and the silicon oxide film and theinsulating film SO5 are polished by CMP to form an insulating filmcorresponding to the interlayer insulating film IL1 on the diffusionregion MD and the diffusion region MS. The subsequent manufacturingsteps are the same as those in FIG. 26 and the subsequent steps of thefirst embodiment.

As described above, in the second embodiment, the diffusion region MDand the diffusion region MS can be formed in the fin FA by a processother than the process of FIG. 16 of the first embodiment.

Further, as in the first embodiment, the diffusion region MD and thediffusion region MS may be formed in the fin FA by the process of FIG.16 by using the insulating film SO3 into which the n-type impurity isintroduced, and further, the diffusion region MD and the diffusionregion MS may be made high in concentration by using the method of thesecond embodiment Such a method is effective when the impurityconcentrations of the diffusion region MD and the diffusion region MSformed by the process of FIG. 16 are not sufficient.

The technique disclosed in the second embodiment can also be applied tothe above-mentioned first to sixth modified example.

Seventh Modified Example

Hereinafter, a semiconductor device of the seventh modified example willbe described with reference to FIG. 40. In the following description,differences from the second embodiment will be mainly described.

In the second embodiment, as described with reference to FIG. 39, thediffusion region MD and the diffusion region MS are formed in the fin FAby diffusing the impurity from the insulating film SO5 into which then-type impurity is introduced into the fin FA.

In the seventh modified example, a diffusion region MD and a diffusionregion MS are formed in the fin FA by an ion implantation method.

FIG. 40 is a cross-sectional view taken along line A-A and line D-Dshown in FIG. 1, and shows the manufacturing process subsequent to FIG.38 of the second embodiment.

As shown in FIG. 40, ion implantation is performed on the exposed fin FAto form a diffusion region MD in the fin FA. As shown in the D-D crosssection, this ion implantation is performed from a direction inclined atan angle θ of about 10 to 45 degrees from a normal to the semiconductorsubstrate SB in a direction (Y direction) orthogonal to the extendingdirection of the fin FA. As a result, since ions are introduced not onlyfrom the upper surface of the fin FA but also from the side surface ofthe fin FA, the diffusion region MD is formed so as to have a relativelyuniform impurity concentration in the fin FA. Although not shown, thediffusion region MS is also formed in the same manner as the diffusionregion MD. Next, heat treatment is performed at about 700 to 1050° C.,whereby impurities contained in the diffusion regions MD and MS arediffused and activated. The subsequent manufacturing process is the sameas that of second embodiment.

Further, similarly to the second embodiment, the diffusion region MD andthe diffusion region MS may be formed in the fin FA by the process ofFIG. 16 using the insulating film SO3 of the first embodiment, andfurther, the diffusion region MD and the diffusion region MS may be madehigh in concentration by using the method of the seventh modifiedexample.

Although the invention made by the present inventors has beenspecifically described based on the embodiment, the present invention isnot limited to the embodiment described above, and various modifiedexamples can be made without departing from the gist thereof.

What is claimed is:
 1. A method of manufacturing a semiconductor device,comprising the steps of: (a) providing a semiconductor substrate; (b)forming a first interlayer insulating film on the semiconductorsubstrate; (c) forming a first opening in the first interlayerinsulating film; (d) forming a dummy pattern inside the first opening;(e) removing a part of the dummy pattern; (f) after the step (e),filling the first opening from which the part of the dummy pattern isremoved with a first gate electrode; (g) after the step (f), removingthe dummy pattern remained in the first opening in the step (e); and (h)filling the first opening from which the dummy pattern is removed in thestep (g) with a second gate electrode.
 2. The method of manufacturing asemiconductor device according claim 1, wherein the step (a) furthercomprises a step of forming a protrusion which is a part of thesemiconductor substrate, and protrudes from an upper surface of thesemiconductor substrate by retreating a part of the upper surface of thesemiconductor substrate, wherein in the step (b), the first interlayerinsulating film is formed so as to cover an upper and side surface ofthe protrusion, and wherein in the step (c), the first opening is formedso as to open a part of the upper and side surface of the protrusion. 3.The method of manufacturing a semiconductor device according to claim 2,further comprising a step of forming an element isolation portion overthe upper surface of the retreated semiconductor substrate between thestep (a) and the step (b), wherein a position of the upper surface ofthe element isolation portion is lower than a position of the uppersurface of the protrusion, wherein, in a plan view, the first opening,the first gate electrode, and the second electrode extend in a firstdirection respectively, and wherein the first and second gate electrodeare formed on the upper and side surface of the protrusion and theelement isolation portion.
 4. The method of manufacturing asemiconductor device according to claim 2, further comprising a step offorming a first insulating film over the side surface of the protrusionbetween the step (b) and the step (c), wherein in the step (e) and (g),the side surface of the protrusion is protected by the first insulatingfilm.
 5. The method of manufacturing a semiconductor device according toclaim 2, wherein the step (a) further comprises steps of: (a1) forming afirst conductive film on the semiconductor substrate, (a2) forming asecond opening in the first conductive film, (a3) inside the secondopening, forming a second insulating film on a side surface of the firstconductive film, (a4) after the step (a3), removing the first conductivefilm, and (a5) after the step (a4), forming the protrusion by echoingthe semiconductor substrate by using the second insulating film as amask.
 6. The method of manufacturing a semiconductor device according toclaim 2, wherein the step (a) further comprises steps of: (a6) forming athird insulating film on the semiconductor substrate, (a7) forming athird opening in the third insulating film, (a8) forming a secondconductive film on a side surface of the third insulating film in thethird opening, (a9) forming a fourth insulating film on the thirdinsulating film and the second conductive film so as to fill the thirdopening, (a10) removing the fourth insulating film formed on the thirdinsulating and the second conductive film so as to remain the secondconductive film and the fourth insulating film formed in the thirdopening, (a11) after the step (a10), removing the second conductivefilm, and (a12) after the step (a11), forming the protrusion by echoingthe semiconductor substrate by using the third and fourth insulatingfilm as a mask.
 7. The method of manufacturing a semiconductor deviceaccording to claim 1, further comprising steps of: between the step (e)and step (f), forming a first gate insulating film inside the firstopening from which the part of the dummy pattern is removed; and betweenthe step (g) and step (h), forming a second gate insulating film insidethe first opening from which the dummy pattern is removed in the step(g), wherein, in the step (f), the first gate electrode is filled in thefirst opening via the first gate insulating film, and wherein, in thestep (g), the second gate electrode is filled in the first opening viathe second gate insulating film.
 8. The method of manufacturing asemiconductor device according to claim 1, wherein, in the step (b),forming the first interlayer insulating film on the semiconductorsubstrate via the fourth insulating film into which an impurity having afirst conductivity type is introduced, wherein, in the step (c), formingthe first opening on the first interlayer insulating film and the fourthinsulating film, and wherein, between the step (c) and the step (d),forming a first diffusion region on the semiconductor substrate bydiffusing the impurity having the first conductivity from the fourthinsulating film to the semiconductor substrate by performing heattreatment.
 9. The method of manufacturing a semiconductor deviceaccording to claim 1, wherein the step (d) further comprises steps of:(d1) inside the first opening, forming a first dummy material on a firstside surface of the first interlayer insulating film, and forming asecond dummy material on a second side surface of the first interlayerinsulating film, the second side surface being opposite to the firstside surface, and (d2) inside the first opening, by forming a thirddummy material between the first dummy material and the second dummymaterial via a fifth insulating film, filling the first opening with thedummy pattern including the first dummy material, the second dummymaterial, the third dummy material, and the fifth insulating film. 10.The method of manufacturing a semiconductor device according to claim 9,wherein the step (d1) further comprises steps of: (d11) forming a thirdconductive film inside the first opening, and (d12) forming the firstand second dummy material being comprised of the third conductive filmby an anisotropic etching process with the third conductive film. 11.The method of manufacturing a semiconductor device according to claim 9,wherein in the step (e), the first dummy material is removed by anisotropic etching process by using the fifth insulating film between thefirst dummy material and the third dummy material as an etching stopperfilm, and wherein in the step (g), the second dummy material, the thirddummy material, and the fifth insulating film are removed.
 12. Themethod of manufacturing a semiconductor device according to claim 9,wherein in the step (e), the first and third dummy material are removedby an etching process on the fifth insulating film between the seconddummy material and the third dummy material as an etching stopper film,and wherein, in the step (g), the second dummy material and the fifthinsulating film are removed.
 13. The method of manufacturing asemiconductor device according to claim 9, wherein the first openingcomprises a plurality of replacement regions extending in a firstdirection, and a connection region extending in a second directionorthogonal to the first direction and connecting the plurality ofreplacement regions, wherein in the step (d1), the first and seconddummy material are formed in the plurality of the replacement regions,and a fourth dummy material integrated with the first dummy material andthe second dummy material is formed in the connection region, wherein inthe step (d2), the third dummy material and the fifth insulating filmare formed in the plurality of replacement regions and are not formed inthe connection region, wherein, between the step (d) and the step (e),further removing the fourth dummy material formed in the connectionregion, and filling the connection region from which the fourth dummymaterial is removed with a second interlayer insulating film.
 14. Themethod of manufacturing a semiconductor device according to claim 1,wherein in a plan view, the first opening comprises a plurality ofreplacement regions extending in a first direction, and a connectionregion extending in a second direction orthogonal to the first directionand connecting the plurality of replacement regions, wherein in the step(d), the dummy pattern is formed in the plurality of the replacementregions and the connection region, and wherein between the step (d) andthe step (e), further removing the dummy pattern formed in theconnection region, and filling the connection region from which thedummy pattern is removed with a third interlayer insulating film. 15.The method of manufacturing a semiconductor device according to claim 1,wherein, in a plan view, the first opening has a replacement regionextending in a first direction, and a first and second power supplyregion extending in the first direction and connecting to thereplacement region, wherein in the step (d), the dummy pattern is formedin the replacement region, the first power supply region, and the secondpower supply region, wherein in the step (e), the dummy pattern in apart of the replacement region and in the first power supply region isremoved, wherein in the step (f), the first gate electrode is formed inthe part of the replacement region and in the first power supply regionis removed, wherein in the step (g), the dummy pattern remained in thereplacement region and the second power supply region in the step (e) isremoved, wherein in the step (h), the second gate electrode is formed inthe replacement region and in the second power supply region where thedummy pattern is removed, and wherein, in a second direction orthogonalto the first direction in a plan view, each of a width of the first andsecond power supply region is smaller than ½ of a width of thereplacement region.
 16. The method of manufacturing a semiconductordevice according to claim 1, further comprising steps of: (i) after thestep (h), removing the first interlayer insulating film; (j) forming asixth insulating film in which an impurity having a first conductivitytype is introduced so as to be contact with the semiconductor substratein a region from which the first interlayer insulating film is removed;and (k) forming a second diffusion region on the semiconductor substrateby diffusing the impurity having the first conductivity from the sixthinsulating film to the semiconductor substrate by performing heattreatment.
 17. The method of manufacturing a semiconductor deviceaccording to claim 1, further comprising steps of: (l) after the step(h), removing the first interlayer insulating film; and (m) forming athird diffusion region having the first conductive type in thesemiconductor substrate by using an ion implantation method in theregion where the first interlayer insulating film is removed.